Appendix E4 ( Used With Permission

          (Unofficial) IBIS Tree Diagram for IBIS Version 4.1
                  Michael Mirmak (Intel Corporation)
   (Based on Work by Ogawa-san of NEC & Bob Ross of Mentor Graphics)
                             2/13/04
                         Revised 3/24/04

		
IBIS Tree (IBIS VERSION 4.1)

  Entries new at versions 2.1, 3.2, 4.0 and 4.1 are noted.

  (m) indicates that keyword or subparameter may occur multiple times.

  (ml) indicates that keyword may occur multiple times at any location.

  * indicates that enumerated selections for the keyword or subparameter
    are provided at the end of the document (other than possible 
    reserved entries NA and NC).


.ibs FILE
---------
  |-- File Data Section
  |   -----------------
  |     |-- [IBIS Ver]               
  |     |-- [Comment Char]          (ml)
  |     |-- [File Name]              
  |     |-- [File Rev]               
  |     |-- [Date] 
  |     |-- [Source]
  |     |-- [Notes]
  |     |-- [Disclaimer]
  |     |-- [Copyright]             (2.1)
  |
  |-- [Component] (m)               (3.2)  Si_location *, Timing_location *
  |   -----------
  |     |-- [Manufacturer]
  |     |-- [Package]                      R_pkg, L_pkg, C_pkg
  |     |-- [Pin]                          signal_name, model_name, R_pin,
  |     |                                  L_pin, C_pin
  |     |-- [Package Model]
  |     |   ----------         
  |     |     |-- [Alternate Package Models]         
  |     |         ----------         
  |     |           |-- [End Alternate Package Models]         
  |     |
  |     |-- [Pin Mapping]           (2.1)  pulldown_ref, pullup_ref,
  |     |                                  gnd_clamp_ref, power_clamp_ref,
  |     |                           (4.1)  ext_ref
  |     |-- [Diff Pin]              (2.1)  inv_pin, vdiff, tdelay_typ,
  |     |                                  tdelay_min, tdelay_max
  |     |-- [Series Pin Mapping]    (3.2)  pin_2, model_name,
  |     |                                  function_table_group
  |     |-- [Series Switch Groups]  (3.2)  On (m), Off (m)
  |     | 
  |     |-- [Node Declarations] (m) (4.1)    
  |     |   ----------         
  |     |     |-- [End Node Declarations] 
  |     |
  |     |
  |     |-- [Circuit Call] (m)      (4.1)  Signal_pin, Diff_signal_pins, 
  |     |                                  Series_pins, Port_map
  |     |   ----------         
  |     |     |-- [End Circuit Call] 
  |
  |
  |-- [Model Selector] (m)          (3.2)
---------------------------------------------------------------------------------
  |
  |-- [Model] (m)                          Model_type *, Polarity *, Enable *,
  |                                        Vinl, Vinh, C_comp, C_comp_pullup, 
  |                                        C_comp_pulldown, C_comp_power_clamp, 
  |                                        C_comp_gnd_clamp
  |                                 (2.1)  Vmeas, Cref, Rref, Vref
  |                                 (4.1)  Rref_diff, Cref_diff
  |   -------
  |     |
  |     |-- [Model Spec]            (3.2)  Vinh, Vinl, Vinh+, Vinh-, Vinl+,
  |     |                                  Vinl-, S_overshoot_high,
  |     |                                  S_overshoot_low, D_overshoot_high,
  |     |                                  D_overshoot_low, D_overshoot_time,
  |     |                                  Pulse_high, Pulse_low, Pulse_time,
  |     |                                  Vmeas, Cref, Rref, Cref_rising, 
  |     |                                  Cref_falling, Rref_rising, 
  |     |                                  Rref_falling, Vref_rising, 
  |     |                                  Vref_falling, Vmeas_rising, 
  |     |                                  Vmeas_falling, 
  |     |                           (4.1)  Rref_diff, Cref_diff
  |     |-- [Receiver Thresholds]   (4.0)  Vth, Vth_min, Vth_max, Vinh_ac, 
  |     |                                  Vinh_dc, Vinl_ac, Vinl_dc,
  |     |                                  Threshold_sensitivity, 
  |     |                                  Reference_supply, Vcross_low,
  |     |                                  Vcross_high, Vdiff_ac, Vdiff_dc, 
  |     |                                  Tslew_ac, Tdiffslew_ac
  |     |-- [Add Submodel] *        (3.2)
  |     |-- [Driver Schedule]       (3.2)
  |     |-- [Temperature Range]     (2.1)
  |     |-- [Voltage Range]
  |     |-- [Pullup Reference]      (2.1)
  |     |-- [Pulldown Reference]    (2.1)
  |     |-- [POWER Clamp Reference] (2.1)
  |     |-- [GND Clamp Reference]   (2.1)
  |     |-- [External Reference]    (4.0) 
  |     |-- [TTgnd]                 (3.2)
  |     |-- [TTpower]               (3.2)
-----------------------------------------------------------------
  |     |-- [Pulldown]
  |     |-- [Pullup]
  |     |-- [GND Clamp]
  |     |-- [POWER Clamp]
  |     |-- [Rgnd]                  (2.1)
  |     |-- [Rpower]                (2.1)
  |     |-- [Rac]                   (2.1)
  |     |-- [Cac]                   (2.1)
  |     |-- [On]                    (3.2)
  |     |-- [Off]                   (3.2)
  |     |-- [R Series]              (3.2)
  |     |-- [L Series]              (3.2)
  |     |-- [Rl Series]             (3.2)
  |     |-- [C Series]              (3.2)
  |     |-- [Lc Series]             (3.2)
  |     |-- [Rc Series]             (3.2)
  |     |-- [Series Current]        (3.2)
  |     |-- [Series MOSFET] (m)     (3.2)  Vds
------------------------------------------------------------------------------
  |     |-- [Ramp]                         dV/dt_r, dV/dt_f,
  |     |                           (2.1)  R_load
  |     |-- [Rising Waveform] (m)   (2.1)  R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
  |     |-- [Falling Waveform] (m)  (2.1)  R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
--------------------------------------------------------------------------------
  |     |-- [Test Data]             (4.0)  Test_data_type *, Driver_model, 
  |     |                                  Driver_model_inv, Test_load
  |     |   -----------
  |     |     |--[Rising Waveform Near]
  |     |     |--[Falling Waveform Near]
  |     |     |--[Rising Waveform Far]
  |     |     |--[Falling Waveform Far]
  |     |     |--[Diff Rising Waveform Near]
  |     |     |--[Diff Falling Waveform Near]
  |     |     |--[Diff Rising Waveform Far]
  |     |     |--[Diff Falling Waveform Far]
  |     |     |--[Test Load]               Test_load_type*, C1_near, Rs_near, 
  |     |                                  Ls_near, C2_near, Rp1_near, 
  |     |                                  Rp2_near, Td, Zo, Rp1_far, Rp2_far,
  |     |                                  C2_far, L2_far, Rs_far, C1_far, 
  |     |                                  V_term1, V_term2, Receiver_model, 
  |     |                                  Receiver_model_inv, R_diff_near, 
  |     |                                  R_diff_far
----------------------------------------------------------------------------
  |     |
  |     |-- [External Model]        (4.1)  Language*, Corner*, Parameters, Ports
  |     |                                  D_to_A, A_to_D
  |     |   ----------         
  |     |     |-- [End External Model]      
  |
  |
  |
  |    
  |-- [Submodel] (m)                (3.2)  Submodel_type *
  |   ----------
  |     |-- [Submodel Spec]                V_trigger_r, V_trigger_f, Off_delay
  |     |-- [POWER Pulse Table]     
  |     |-- [GND Pulse Table]     
  |     |-- [Pulldown]
  |     |-- [Pullup]
  |     |-- [GND Clamp]
  |     |-- [POWER Clamp]
  |     |-- [Ramp]                         dV/dt_r, dV/dt_f, R_load
  |     |-- [Rising Waveform] (m)          R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
  |     |-- [Falling Waveform] (m)         R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
  |    
  |
  |-- [External Circuit] (m)        (4.1)  Language*, Corner*, Parameters, Ports
  |                                        D_to_A, A_to_D
  |   ----------         
  |     |-- [End External Circuit]  
  |
  |
  |      
  |-- [Define Package Model] (m)    (2.1)
  |   ----------------------
  |     |-- [Manufacturer]
  |     |-- [OEM]
  |     |-- [Description]
  |     |-- [Number Of Sections]
  |     |-- [Number Of Pins]
  |     |-- [Pin Numbers]                  
  |     |                           (3.2)  Len (m), L (m), R (m), C (m),
  |     |                           (3.2)  Fork (m), Endfork (m)
  |     |-- [Model Data]
  |     |   ------------
  |     |     |-- [Resistance Matrix]      Banded_matrix, Sparse_matrix,
  |     |     |                            Full_matrix
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |-- [Inductance Matrix]      Banded_matrix, Sparse_matrix,
  |     |     |                            Full_matrix
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |-- [Capacitance Matrix]     Banded_matrix, Sparse_matrix,
  |     |     |                            Full_matrix
  |     |     |   --------------------    
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |-- [End Model Data]
  |     |-- [End Package Model]
  |
  |-- [End] 


.pkg FILE                           (2.1)
---------
  |-- File Data Section             (2.1)             
  |   -----------------
  |     |-- [IBIS Ver]
  |     |-- [Comment Char] (ml)
  |     |-- [File Name]
  |     |-- [File Rev]                  
  |     |-- [Date]
  |     |-- [Source]
  |     |-- [Notes]
  |     |-- [Disclaimer]
  |     |-- [Copyright]
  |
  |-- [Define Package Model] (m)    (2.1)
  |   ----------------------
  |     |-- [Manufacturer]
  |     |-- [OEM]
  |     |-- [Description]
  |     |-- [Number Of Sections]
  |     |-- [Number Of Pins]
  |     |-- [Pin Numbers]                  
  |     |                           (3.2)  Len (m), L (m), C (m), R (m),
  |     |                           (3.2)  Fork (m), Endfork (m)
  |     |-- [Model Data]
  |     |   ------------
  |     |     |-- [Resistance Matrix]      Banded_matrix, Sparse_matrix,
  |     |     |                            Full_matrix
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |-- [Inductance Matrix]      Banded_matrix, Sparse_matrix,
  |     |     |                            Full_matrix
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |-- [Capacitance Matrix]     Banded_matrix, Sparse_matrix,
  |     |     |                            Full_matrix
  |     |     |   --------------------    
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |-- [End Model Data]
  |     |-- [End Package Model]
  |
  |-- [End]


.ebd FILE                           (3.2)         
---------
  |-- File Data Section             (3.2)
  |   -----------------
  |     |-- [IBIS Ver]
  |     |-- [Comment Char] (ml)               
  |     |-- [File Name]
  |     |-- [File Rev]
  |     |-- [Date]
  |     |-- [Source]
  |     |-- [Notes]                       
  |     |-- [Disclaimer]
  |     |-- [Copyright]
  |
  |-- [Begin Board Description]     (3.2)
  |   ----------------------
  |     |-- [Manufacturer]
  |     |-- [Number of Pins]
  |     |-- [Pin List]                      signal_name
  |     |-- [Path Description] (m)          Len (m), L (m), R (m), C (m), 
  |     |                                   Fork (m), Endfork (m), 
  |     |                                   Pin (m), Node (m)
  |     |-- [Reference Designator Map]
  |     |-- [End Board Description]
  |
  |-- [End]


* Available Selections

  [Add Submodel]                    (3.2)   Mode column selections
        Driving
        Non-Driving
        All

  Si_location                       (3.2)
        Pin
        Die

  Timing_location                   (3.2)
        Pin
        Die

  Polarity              
        Non-Inverting
        Inverting

  Enable
        Active-High
        Active-Low

  Language                          (4.1)
        SPICE
        VHDL-AMS
        Verilog-AMS

  Corner                            (4.1)
        Typ
        Min
        Max

  Model_type
	3-state
        3-state_diff                (4.1)
	3-state_ECL                 (3.2)            
	I/O
        I/O_diff                    (4.1)
	I/O_ECL                     (2.1)
	I/O_open_drain              (2.1)
	I/O_open_sink               (2.1)
	I/O_open_source             (2.1)
	Input
        Input_diff                  (4.1)
	Input_ECL                   (2.1)
	Open_sink                   (2.1)
	Open_drain 
 	Open_source                 (2.1)           
	Output 
        Output_diff                 (4.1)
	Output_ECL                  (2.1)
	Series                      (3.2)
	Series_switch               (3.2)
	Terminator                  (2.1)

  Submodel_type                     (3.2)
	Bus_hold
	Dynamic_clamp
        Fall_back                   (4.0)

  Test_data_type                    (4.0)
        Single_ended
        Differential

  Test_load_type                    (4.0)
        Single_ended
        Differential




